Jx CPU Core

General Description

The J32 core is an optimized, synthesizable CPU core, compatible with the Hitachi SHcompact instruction specification. Having a full Harvard architecture, the CPU core is designed to integrate with a memory or cache controller to arbitrate between instruction and data access cycles. The J32 pipeline retires 1 instruction per cycle for most common instructions. SHcompact is designed to enable efficient code generation from high level languages such as C, typically resulting is an instruction memory footprint of less than half the size for common algorithms and applications compared with the ARM or MIPS architectures. The J32 core produces efficient external memory access patterns to reduce external memory traffic and reduced memory bandwidth requirements.

The J32 most closely approximates the Hitachi/Renesas SH-2 CPU core, with added functionality for signal processing and operating system support. The bus interface is completely unique. Its full Harvard architecture provides the flexibility to create gate count efficient systems of varying complexity, as required by the particular application. Retaining full instruction set backward compatibility with SH Compact allows the J32 to be used with the full set of rich tool sets available from GNU and third parties.

Comparison with other options

The J32 core compares favorably with the ARM M4 core, and provides a more flexible, high performance and low cost alternative. No per-project costs means a path to future designs.

Foundry Integration

J32 is process independent, and a broad range of process technologies from 0.35μm to the smallest geometries are available on logic, mixed signal/RF CMOS, high voltage, embedded memory, and CIS technology processes.