GNSS Receiver Engine

This IP block consists of

- An open, auditable hardware baseband IP core

- Interface to a CoreSemi DSP for low power, fast Time To First Fix

- Configurable channelization, depending on the application

- Optional digital antenna interface, with automatic cable length correction for accurate time recovery

- A firmware stack for dedicated J-Core J1 embedded processors or J2/J32 host processing

- Suitable for use in systems requiring trusted time and location

GNSS Software

The GNSS driver and tracking software consumes very little CPU, and is suitable for low power applications. In connected or fixed location timing applications, APGS provides fast TTFF while consuming very little power. The software is all portable ANSI C and compiles to less than 128kbytes for compact embedded systems.

Other Components

The GNSS time and location cores can be used with the Jx development platform, to allow for rapid application development