Jx Secure SoC

Features

150MHz, dual J-Core 32 bit RISC CPU in SMP configuration
8kB instruction cache + 8kB data cache per CPU
Core Semiconductor Trusted Compute Engine
Boot ROM, SRAM, MMU, DMAC, DDR controller, dual EMAC, GPIO, dual SPI I/F, dual UARTs, dual I²C I/F, JTAG

Advantages

Provably secure due to independently auditable, open source silicon
Tamper resistant hardware root-of-trust
Hardware enforced boot-time & runtime security
Well supported development tool ecosystem

Datasheet

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